`timescale 1 ns / 1 ps
module tb
(

);

parameter PERIOD = 20 ;


reg      pll_rst;
reg      test_rst;
wire   	tx_rx;
wire		clk_10M;
wire		pll_locked;


wire     rst=!pll_locked;


wire		[1:0]	 tx_rdy;

reg      [8:0]  tx_data;
reg		[7:0]  frame_len;//frame length 
reg		[3:0]  frame_st;
reg             frame_end;


reg				 tx_nce;
reg				 tx_nwe;
reg		[7:0]  tx_rd_addr;
reg             tx_rd_ab;

wire		[8:0]  tx_rd_data;
				 

wire    [8:0]   tx_rd_addr_ab=  {tx_rd_ab,tx_rd_addr};


reg inclk ;

   initial begin
      inclk = 1'b0;
      #(PERIOD/2);
      forever
         #(PERIOD/2) inclk = ~inclk;
   end


reg test_clk ;

   initial begin
	   test_clk = 1'b1;
      #3 ;
		test_clk = 1'b0;
      #(PERIOD/6);
      forever
         #(PERIOD/6) test_clk = ~test_clk;
   end

	

	initial begin
	test_rst=1'b1;
	pll_rst=1'b1;
	tx_data=0;
	#50 pll_rst=1'b0;
	test_rst=1'b0;
	end
	
	
	
always@(posedge test_clk or posedge test_rst)
if(rst) begin
   tx_rd_ab	  <=1'b0;
	tx_rd_addr <=255;
	tx_nce	  <=1'b1;
	tx_nwe		<=1'b1;
	frame_len	<=0;
	tx_data		<=0;
	frame_end<=1'b0;
	frame_st		<=0;  //frame state machine
end
else  case(frame_st)
0:begin
	tx_rd_ab	   <=1'b0;
	tx_rd_addr  <=255;
	tx_nce		<=1'b1;
	tx_nwe		<=1'b1;		
	tx_data		<=0;
	frame_end<=1'b0;
	if((tx_rdy[1]==1'b1)|(tx_rdy[0]==1'b1))
	frame_st		<=1;
   end
	

	
1:begin  //start 1
   tx_nce		<=1'b0;
	tx_nwe		<=1'b1;	
    frame_end	<=1'b0;	
   if(tx_rd_data[8]==1'b0)begin
	frame_st		<=2;
  end	
end


2:begin  //start 1
	frame_len	<=frame_len+1'b1;
	frame_st		<=3;
	tx_nce		<=1'b0;
	tx_nwe		<=1'b1;
	tx_rd_addr  <=0;
	frame_st<=4;
	tx_data		<=9'h00;
end

3:begin
	frame_len<=frame_len+1;
	tx_data<=tx_data+1;
	tx_rd_addr  <=tx_rd_addr+1'b1;
	tx_nce		<=1'b0;
	tx_nwe		<=1'b1;
	frame_st<=4;
	if(frame_len==16)begin
		frame_end<=1'b1;
		tx_data		<={1'b1,frame_len};  //K28.1    001_11100= 0011_1100
		tx_rd_addr  <=8'd255;
	end
end
4:begin
	frame_st		<=5;
	tx_nce		<=1'b0;
	tx_nwe		<=1'b0;
	end
5:begin
	frame_st		<=6;
	tx_nce		<=1'b0;
	tx_nwe		<=1'b0;	
   end
	
6:begin
	frame_st		<=7;
	tx_nce		<=1'b0;
	tx_nwe		<=1'b0;	
   end	
7:begin
   frame_st		<=8;
	tx_nce		<=1'b0;
	tx_nwe		<=1'b1;	
  end	
8:begin
	frame_st		<=9;
	tx_nce		<=1'b1;
	tx_nwe		<=1'b1;	
   end 
9:begin
  if(frame_end) begin
  frame_st		<=1;
  frame_len	<=0;
  tx_rd_ab	  <=~tx_rd_ab;
  tx_rd_addr  <=255;
  end
  else
  frame_st		<=3;
end
default:frame_st<=0;
endcase














reg				rx_nce;
reg				rx_noe;
reg				rx_nwe;
wire		[8:0] rx_data;
reg		[7:0] rx_data_out;
wire				rx_rdy;	
reg		[7:0] rx_addr_r; 
reg				rx_toggle;
reg		[7:0] rx_len;
reg      [2:0] recv_st;

wire		[8:0] rx_addr={rx_toggle,rx_addr_r};


always@(posedge test_clk or posedge test_rst)

if(test_rst) begin
	rx_nce		<=1'b1;
	rx_noe		<=1'b1;
	rx_nwe		<=1'b1;
	rx_toggle	<=1'b0;
	rx_addr_r	<=255;  
	rx_len		<=0;
	rx_data_out	<=0;
	recv_st		<=0;
end

else case(recv_st)
0: begin
	rx_nce		<=1'b1;
	rx_noe		<=1'b1;
	rx_nwe		<=1'b1;
	rx_toggle	<=1'b0;
	rx_addr_r	<=255; 
	rx_len		<=0;
	rx_data_out	<=0;
	if(rx_rdy)
	recv_st	<=1;
end
1:begin
	rx_nce	<=1'b0;	
	rx_noe	<=1'b0;
	rx_nwe	<=1'b1;
	rx_len	<=0;
	recv_st	<=2;
  end
2:begin
	rx_nce	<=1'b0;	
	rx_noe	<=1'b0;
	rx_nwe	<=1'b1;
	rx_len	<=0;
	recv_st	<=3;
   end  
3:begin
		rx_nce	<=1'b1;	
		rx_noe	<=1'b1;
		rx_nwe	<=1'b1;
		if(rx_data[8]) begin
			rx_len	<=rx_data[7:0];
			rx_addr_r	<=rx_addr_r+1;
			recv_st	<=4;
		end
		else begin
			rx_addr_r	<=255;
			rx_toggle<=~rx_toggle;
			recv_st	<=1;
		end
	end
4:begin
	rx_nce	<=1'b0;	
	rx_noe	<=1'b0;
	rx_nwe	<=1'b1;
	recv_st	<=5;
   end
5:begin
	rx_nce	<=1'b0;	
	rx_noe	<=1'b0;
	rx_nwe	<=1'b1;
	rx_len	<=rx_len-1'b1;
	recv_st	<=6;
   end	
6:begin
	rx_nce		<=1'b1;	
	rx_noe		<=1'b1;
	rx_nwe		<=1'b1;
	rx_data_out	<=rx_data[7:0];
	if(rx_len==0)
		recv_st		<=7;
	else
		recv_st		<=4;
end
7:begin	
	rx_addr_r	<=255;
	if(rx_rdy) begin
		rx_toggle<= ~rx_toggle;
		recv_st	<=1;
	end
  end
 default:recv_st	<=0;
endcase

lvds_top   lvds_top_inst
(
.inclk			(inclk),
.pll_rst			(pll_rst),
.tx_nce			(tx_nce),
.tx_nwe			(tx_nwe),
.tx_rdy			(tx_rdy),
.tx_data			(tx_data),
.tx_rd_addr_ab (tx_rd_addr_ab),
.tx_rd_data		(tx_rd_data),
.tx				(tx_rx),




.rx				(tx_rx),
.rx_nce			(rx_nce),
.rx_noe			(rx_noe),
.rx_nwe			(rx_nwe),
.rx_data			(rx_data),
.rx_rdy			(rx_rdy),		
.rx_addr			(rx_addr),  


.clk_10M			(clk_10M),
.pll_locked		(pll_locked)

);


endmodule

